The present invention relates, generally, to interconnecting microelectronic devices and supporting substrates, and more particularly relates to a method and apparatus for compliantly interconnecting microelectronic devices and supporting substrates while substantially obviating the problems encountered due to their differences in the thermal coefficients of expansion.
Semiconductor chips typically are connected to external circuitry through contacts on a surface of the chip. To save area on a supporting substrate, such as a printed circuit board, these chips are typically directly connected/soldered to the substrates and from there connected to external circuitry on other parts of the substrate. The contacts on the chip are generally either disposed in regular grid-like patterns, substantially covering the front surface of the chip (commonly referred to as an xe2x80x9carea arrayxe2x80x9d) or in elongated rows extending parallel to and adjacent each edge of the chip front surface. The various prior art processes for making the interconnections between the semiconductor chip contacts and the supporting substrate use prefabricated arrays of leads/discrete wires, solder bumps or combinations of both. One or more integrated circuit (xe2x80x9cICxe2x80x9d) chips are typically mounted in a package or microelectronic device, such as a ceramic multichip module, that is suited for attachment by soldering to a wiring substrate, such as a printed wiring board or module. The body of the microelectronic device may be comprised of a molded plastic or ceramic material. Many of the techniques for solder attachment run into problems because of the thermal expansion mismatch between the material the microelectronic device is composed of and the material the supporting substrate is made of, such as a printed circuit board. In other words, when heat is applied to the microelectronic device/substrate combination, they both expand; and when the heat is removed, the device and the substrate both contract. The problem that arises is that the device and the substrate expand and contract at different rates and at different times, thereby stressing the interconnections between them.
In attempting to use the area on printed circuit boards more efficiently, IC manufacturers have recently been switching from larger, more cumbersome interconnection conventions, such as pin grid arrays (xe2x80x9cPGAsxe2x80x9d) and the perimeter leaded quad flat packs (xe2x80x9cQFPsxe2x80x9d), to smaller conventions, such as ball grid arrays (xe2x80x9cBGAsxe2x80x9d). Using BGA technology, microelectronic devices are typically interconnected with their supporting substrates using solder connections, such as with xe2x80x9cflip-chipxe2x80x9d technology. However, when solder alone is used to interconnect the microelectronic device""s contacts to the substrate, the columns of solder are generally designed to be short to maintain the solder""s structural integrity. This results in minimal elastic solder connection properties which further results in increased susceptibility to solder cracking due to fatigue brought on by the thermal cycling (heating and cooling cycles of the device/substrate).
An interconnection solution put forth in U.S. Pat. No. 4,642,889, entitled xe2x80x9cCompliant Interconnection and Method Thereforxe2x80x9d issued Apr. 29, 1985 to Grabbe seeks to alleviate the aforementioned solder cracking problem by embedding wires within each solder column to reinforce the solder thereby allowing higher solder pedestals and more elasticity. Another solution includes spirally wrapping wire around the outside of the solder. A further solution put forth includes providing a combination of solder and high lead solder, as found in U.S. Pat. No. 5,316,788, entitled xe2x80x9cApplying Solder to High Density Substratesxe2x80x9d issued to Dibble et al. All of these prior art solutions are aimed at increasing the compliancy of the interconnections in order to reduce the shear stress endured by the interconnections because of the thermal cycling. However, as microelectronic devices are reduced in size, the number of devices packed into a given area will be greater. The heat dissipated by the each of these devices will have a greater effect on the surrounding devices and will thus increase the need for a highly compliant interconnection scheme for each device. Further, as the number of device interconnections increases, as is the case when chips are integrated into multichip modules, the overall rigidity of the total interconnection also increases thereby again increasing the need for a highly compliant interconnection scheme. None of the aforementioned prior solutions provides an interconnection scheme which is compliant enough to effectively deal with these problems.
Several inventions, commonly assigned to the assignee of the present invention, deal effectively, but specifically differently, with the thermal cycling problem. For example, U.S. Pat. No. 5,148,266 discloses improvements in semiconductor chip assemblies and methods of making the same. As set forth in the ""266 patent, a semiconductor chip can be connected to a substrate using a sheet-like, and preferably flexible, interposer. The interposer overlies the top, contact-bearing surface of the chip. A first surface of the interposer faces towards the chip whereas a second surface faces away from the chip. Electrical terminals are provided on the second surface of the interposer, and the interposer is also provided with apertures extending through it. Flexible leads extend through these apertures between contacts on the chip and the terminals on the second surface of the interposer: The terminals can be bonded to a substrate. Because the terminals are movable relative to the contacts on the chip, the arrangements described in the ""266 patent provide excellent resistance to thermal cycling. The interposer disclosed in the ""266 patent may also include a compliant layer disposed between the terminals and the chip.
Further, WIPO Publication No. 9403036 published on Feb. 3, 1994, also commonly owned by the present assignee, discusses semiconductor chip mounting devices. As set forth in the ""036 application, an interposer is used which has a gap extending from a first surface to a second surface. One or more conductive leads are then secured to the first surface of the interposer extending across the gap and connected at a first end to a terminal on the interposer. A second end of the lead may then be displaced downwardly to connect to a contact on a semiconductor chip. The lead may have a frangible section that is designed to break during the bonding process, leaving one end of the lead free to be displaced downwardly to make contact with the chip. Further, a compliant, dielectric bottom layer may be coupled between the interposer and the chip to provide stand off and added compliancy.
Despite the positive results of the aforementioned commonly owned inventions, still further improvements would be desirable.
The present invention provides a method and apparatus for compliantly interconnecting surface mount microelectronic devices to supporting substrates, such as printed circuit boards, to accommodate for the typically large thermal expansion mismatch between the device and the substrate.
More specifically, one aspect of the present invention provides a method which compliantly interconnects microelectronic devices and ceramic modules to supporting substrates by providing a compliant intermediate interconnection scheme that counterbalances thermal cycling problems. In one embodiment of the present invention, a flexible film circuit element (referred hereinafter as xe2x80x9cflex circuitxe2x80x9d) having an array of bonding holes is used. On a first side of the flex circuit, an array of conductive base pads are situated such that there is a bonding hole between two successive base pads. A plurality of conductive leads is next employed to electrically connect the base pads across the bonding hole. Thus, each conductive lead bridges each bonding hole to connect the two successive base pads to create electrically connected base pad/bonding hole/conductor rows. Flex circuit contact pads are next coupled to the exposed surface of each of the base pads. Further, a highly conductive joining layer, such as gold or gold plated on to nickel, is either coupled to the underside of or completely around the conductive lead within the bonding hole. The base pad/bonding hole/conductor rows facilitate electroplating of the leads and contact pads during the fabrication process.
Each of the conductive leads has a frangible or xe2x80x9cweakxe2x80x9d point within or near the perimeter of each of the bonding holes and allows the lead to be cleanly broken or fractured in response to a orthogonally directed force. The frangible point can be created by any suitable means, such as scoring the lead, creating a xe2x80x9cthinxe2x80x9d area in the lead either in width or depth or not coupling the highly conductive joining layer to a small portion of the underside of the lead.
The microelectronic device has an array of device contact pads each of which is placed opposite a respective bonding hole when the device""s surface and a second side of the flex circuit are placed opposite one another. A plurality of compliant elastomer pads or buttons are sandwiched between the device and the second side of the flex circuit and adhere the device and the flex circuit together. Typically, the compliant pads are located under each flex circuit contact pad to provide structural support when the flex circuit contact pads are eventually connected to the contacts on a circuit board.
Each of the frangible points in the conductive leads is then cleanly broken, generally using a device known as a forming tool, and the leads are bent into electrical contact with their respective device contact pads. The leads and device contact pads are then coupled using a suitable coupling technique, such as ultrasonic, thermosonic or compression bonding. In a preferred embodiment, the xe2x80x9copenxe2x80x9d area between the flex circuit, the microelectronic device and the compliant pads may then be filled with uncured elastomer, which is then cured. This last step provides added support for the leads and the compliant pads.
Another aspect of the present invention provides a compliant microelectronic device mounting device which effectively counterbalances problems due to thermal expansion mismatch between the microelectronic device and a supporting substrate. In one embodiment, a flex circuit having at least one bonding hole extending through from a first to a second side is used. The first side of the flex circuit further has at least one conductive lead and at least two contact pads, such that each lead bridges a respective bonding hole to connect two successive contact pads. Each conductive lead further has a frangible point within or near a perimeter of its respective bonding hole. A compliant layer is then placed between the flex circuit and the microelectronic device. Typically, the compliant layer includes an array of compliant pads or buttons. These pads need not be positioned anywhere in particular, but are generally positioned underneath each flex circuit contact pad. A forming tool is generally used to break each lead at its frangible point so that the lead may be connected to an opposing device contact pad. A liquid may be injected in the space between the compliant pads and cured to give added support to the leads and the compliant pads.
The foregoing and other objects and advantages of the present invention will be better understood from the following Detailed Description of a Preferred Embodiment, taken together with the attached Figures.